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ENGR00181194 IPUv3:Correct pixel clock definition and register
authorLiu Ying <Ying.Liu@freescale.com>
Sat, 28 Apr 2012 05:24:45 +0000 (13:24 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:34:32 +0000 (08:34 +0200)
commit14ed7fff9063f2dc5cbee2db178439b8e6ce6c79
tree7a73a1564a85ccdbc08c4bad361a7c9ce828215ctree | snapshot
parent3d3da8fdb296954b91f848f674043ef16f2660e8commit | diff
ENGR00181194 IPUv3:Correct pixel clock definition and register

MX6Q has 2 IPUs, each IPU has 2 DIs, so there are totally 4
different pixel clocks. This patch adds maximal pixel clock
number from 2 to 4. Also, the patch fixes potential build
warning caused by the overflow on ipu_lookups structure in case
MXC_IPU_MAX_NUM is 1.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
drivers/mxc/ipu3/ipu_common.c diff | blob | history
drivers/mxc/ipu3/ipu_disp.c diff | blob | history
drivers/mxc/ipu3/ipu_prv.h diff | blob | history
Linux kernel for KaRo TX COM modules