ENGR00171087 [MX6]Need to add L1 Icache invalidate

ENGR00171087 [MX6]Need to add L1 Icache invalidate

As there might be dirty data line on any core of MX6
SOC when power on or reset, we need to do L1 I-cache
invalidation in the resume process and start up
process for all cores.

This is very important for us, as not all of the hardware
will do cache invalidation during power on or reset, so
we need to do the invalidation for all cache(L1, L2,
I and D) before first time enabling. Please keep in mind.

Signed-off-by: Anson Huang <b20788@freescale.com>