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(parent: 44ab8cc) | patch
drm/nvc0/pm: restrict pll mode to clocks that can actually use it
authorBen Skeggs <bskeggs@redhat.com>
Mon, 6 Feb 2012 23:59:54 +0000 (09:59 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Tue, 13 Mar 2012 07:14:58 +0000 (17:14 +1000)
commit1ae73f2f16f1a905ada71e2a190d5760b4f17ed8
tree10ee30114c0333feed5b80bffb571d9b935c70d0tree | snapshot
parent44ab8cc56c45ca781371a4a77f35da19cf5db028commit | diff
drm/nvc0/pm: restrict pll mode to clocks that can actually use it

Fixes reclocking failure on some chips where we attempted to set PDAEMON
to PLL mode.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvc0_pm.c diff | blob | history
Beck SC1x5 Kernel