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(parent: 73de5c8) | patch
clk: meson: add mpll support
authorMichael Turquette <mturquette@baylibre.com>
Tue, 7 Jun 2016 06:16:17 +0000 (23:16 -0700)
committerMichael Turquette <mturquette@baylibre.com>
Thu, 23 Jun 2016 01:02:59 +0000 (18:02 -0700)
commit1c50da4f27cbfb588b59684b55eb7a087bb26ed1
tree476a4b396e86fb59ad46baa1e2156d25a36003aatree | snapshot
parent73de5c8bcf4924faf5d57c3d626b01a04ed1ee41commit | diff
clk: meson: add mpll support

MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and
GXBB they appear to be only derived from fixed_pll.

Add support for these clock types so that they can be added to their
respective drivers.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
drivers/clk/meson/Makefile diff | blob | history
drivers/clk/meson/clk-mpll.c [new file with mode: 0644] blob
drivers/clk/meson/clkc.h diff | blob | history
Beck SC1x5 Kernel