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Hexagon: Implement basic cache-flush support
authorRichard Kuo <rkuo@codeaurora.org>
Wed, 14 Sep 2011 00:50:34 +0000 (10:50 +1000)
committerStephen Rothwell <sfr@canb.auug.org.au>
Wed, 14 Sep 2011 00:50:34 +0000 (10:50 +1000)
commit1cc71b8d41ccc954b0213a4fb33ec752b5f30f45
treeb387bcd754f560cb70eaa682090bf9ab0ad07e3etree | snapshot
parentced07515d13b6aeb726b25313fc12b3bbc96eedbcommit | diff
Hexagon: Implement basic cache-flush support

We have separate I/D caches.  Data caches are physically indexed.

Signed-off-by: Richard Kuo <rkuo@codeaurora.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
arch/hexagon/include/asm/cache.h [new file with mode: 0644] blob
arch/hexagon/include/asm/cacheflush.h [new file with mode: 0644] blob
arch/hexagon/mm/cache.c [new file with mode: 0644] blob
Linux kernel for KaRo TX COM modules