ASoC: fsl_spdif: Use clk_set_rate() for spdif root clock only

ASoC: fsl_spdif: Use clk_set_rate() for spdif root clock only

The clock mux for the Freescale S/PDIF controller has eight clock sources
while most of them are from other moudles and even system clocks that do
not allow a rate-changing operation.

So we here only allow the clk_set_rate() and clk_round_rate() happened to
spdif root clock, the private clock for S/PDIF controller.

Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 9c6344b3fa547ce7ec78da95134d92d9f9309b31)