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(parent: 97bf6af) | patch
clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks
authorDoug Anderson <dianders@chromium.org>
Thu, 4 Dec 2014 21:33:05 +0000 (13:33 -0800)
committerHeiko Stuebner <heiko@sntech.de>
Sun, 21 Dec 2014 13:15:26 +0000 (14:15 +0100)
commit221dfbae2b33868267d979a113079678dcd4dab3
treeb7212cc740653ce2342edc3e1390e30727f7b4d1tree | snapshot
parent97bf6af1f928216fd6c5a66e8a57bfa95a659672commit | diff
clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks

We'd like to be able to set the clock rate of the sclk_uart clocks and
actually be able to achieve clock rates greater than 24MHz.  To do
this we need to be able to pass rate changes upward.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3288.c diff | blob | history
Beck SC1x5 Kernel