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perf/x86: Add Intel LBR MSR definitions
authorStephane Eranian <eranian@google.com>
Thu, 9 Feb 2012 22:20:52 +0000 (23:20 +0100)
committerIngo Molnar <mingo@elte.hu>
Mon, 5 Mar 2012 13:55:39 +0000 (14:55 +0100)
commit225ce53910edc3c2322b1e4f2ed049a9196cd0b3
treeadd1a7795fd5120d17cef078e1d457199e5e3608tree | snapshot
parentbce38cd53e5ddba9cb6d708c4ef3d04a4016ec7ecommit | diff
perf/x86: Add Intel LBR MSR definitions

This patch adds the LBR definitions for NHM/WSM/SNB and Core.
It also adds the definitions for the architected LBR MSR:
LBR_SELECT, LBRT_TOS.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1328826068-11713-3-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/include/asm/msr-index.h diff | blob | history
arch/x86/kernel/cpu/perf_event_intel_lbr.c diff | blob | history
Beck SC1x5 Kernel