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ARM: dt: tegra seaboard: fix I2C2 SCL rate
authorStephen Warren <swarren@nvidia.com>
Thu, 26 Apr 2012 17:19:03 +0000 (11:19 -0600)
committerStephen Warren <swarren@nvidia.com>
Thu, 3 May 2012 20:49:08 +0000 (14:49 -0600)
commit22bd1f7ef40a1c0f2ba796ba7cd80013adcb835d
tree050f3475bfeeca1aa5d24923bc8d3d108a938afdtree | snapshot
parentb46b0b54dea200973ce380369beb192b136d8934commit | diff
ARM: dt: tegra seaboard: fix I2C2 SCL rate

This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/boot/dts/tegra-seaboard.dts diff | blob | history
Beck SC1x5 Kernel