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clk: samsung: exynos3250: Add UART2 clock
authorPankaj Dubey <pankaj.dubey@samsung.com>
Thu, 31 Mar 2016 02:47:59 +0000 (11:47 +0900)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Thu, 31 Mar 2016 10:25:49 +0000 (12:25 +0200)
commit27c0efedcf1be044dd638784189de816382f3f43
treefa26a9a02d0da8b66e7cb9d502d41779637badf2tree | snapshot
parentfd00bbcddb59c4866e7c985e30f663b62cfc2588commit | diff
clk: samsung: exynos3250: Add UART2 clock

This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos3250.c diff | blob | history
Beck SC1x5 Kernel