ENGR00220297 [MX6SL]: Fix AHB clock not correct after kernel boot

ENGR00220297 [MX6SL]: Fix AHB clock not correct after kernel boot

1. Fix AHB_CLK is not right after system up. ahb_clk is 49.5MHz
after system up. It should be 132MHz.
2. Remove the voltage changes for VDDSOC_CAP since there are vddarm
voltage changed in CPUFREQ and vddsoc voltage and vddarm voltage
should meet the constraint condition: VDDSOC > VDDARM - 50mV. Therefore
VDDSOC voltage changes will be implemented in CPUFREQ.

Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>