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ENGR00219164: caam: limit AXI pipeline depth = 1 on mx6 for errata
authorSteve Cornelius <steve.cornelius@freescale.com>
Wed, 1 Aug 2012 23:09:27 +0000 (16:09 -0700)
committerOliver Wendt <ow@karo-electronics.de>
Mon, 30 Sep 2013 12:12:37 +0000 (14:12 +0200)
commit2bd085f106feddb015277c2f167147bb711e3f05
treeba1e30447e031ae671b29ce8fd107823f82062batree | snapshot
parent1bf53f8e93a0f0d5905b6688c60c31e713c09e08commit | diff
ENGR00219164: caam: limit AXI pipeline depth = 1 on mx6 for errata

This patch limits AXI pipeline depth to 1 as a workaround for errta
TKT134813, the write
concurrency problem on mx6.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
drivers/crypto/caam/ctrl.c diff | blob | history
Linux kernel for KaRo TX COM modules