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ARM: l2c: zynq: remove cache size override
authorRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 19 Mar 2014 12:22:34 +0000 (12:22 +0000)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 29 May 2014 23:50:28 +0000 (00:50 +0100)
commit2c4133c5d0e98ea5c7faca780e2b846d10f430c8
treeb4f5157e92e151eac1988e07862fd9cd9fc0db69tree | snapshot
parentb28dd4ac66de15c48b00184b63180094f2f7fb45commit | diff
ARM: l2c: zynq: remove cache size override

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mach-zynq/common.c diff | blob | history
Linux kernel for KaRo TX COM modules