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(parent: a064b5c) | patch
ARM: tegra: change pll_p_out4's rate to 24MHz
authorStephen Warren <swarren@nvidia.com>
Thu, 12 Apr 2012 20:13:05 +0000 (14:13 -0600)
committerStephen Warren <swarren@nvidia.com>
Mon, 16 Apr 2012 17:00:27 +0000 (11:00 -0600)
commit3c5dc200bbd3621c56766f7fd41d3269f64ad403
tree57230d2db3deb9232a12e161c291a945948974b7tree | snapshot
parenta064b5c7cbd98acedf5239d55e9ed30f463c42f5commit | diff
ARM: tegra: change pll_p_out4's rate to 24MHz

pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.

Remove board-paz00.c's now-duplicate initialization of this clock.

Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/mach-tegra/board-paz00.c diff | blob | history
arch/arm/mach-tegra/common.c diff | blob | history
Linux kernel for KaRo TX COM modules