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(parent: 8615009) | patch
MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs.
authorDavid Daney <david.daney@cavium.com>
Mon, 29 Jul 2013 22:07:04 +0000 (15:07 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 5 Aug 2013 11:35:46 +0000 (13:35 +0200)
commit3cf24219a72e6fb5ddb5d178c517243c02f76c43
treee30a934b284ea9b0ae16283a06c5b69562d4bf02tree | snapshot
parent86150099971747d651d0b812651135709d772be2commit | diff
MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5638/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/c-octeon.c diff | blob | history
Linux kernel for KaRo TX COM modules