The AT91 PLL rate configuration is done by configuring a multiplier/divider
pair.
The previous calculation was over-complicated (and apparently buggy).
Simplify the implementation and add some comments to explain what is done
here.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reported-by: Gaël PORTAY <gael.portay@gmail.com> Tested-by: Gaël PORTAY <gael.portay@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>