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(parent: 5b795d0) | patch
ARM: tegra: config the polarity of the request of sys clock
authorJoseph Lo <josephl@nvidia.com>
Mon, 12 Aug 2013 09:40:01 +0000 (17:40 +0800)
committerStephen Warren <swarren@nvidia.com>
Mon, 12 Aug 2013 18:22:39 +0000 (12:22 -0600)
commit444f9a8030ecda8dedd374fc3efed03d9f20e9cb
tree396cc998a2265b70ef00d80c2b88f4f62132fe56tree | snapshot
parent5b795d051c61862cebf4f1d55edab6e9b3383b44commit | diff
ARM: tegra: config the polarity of the request of sys clock

When suspending to LP1 mode, the SYSCLK will be clock gated. And different
board may have different polarity of the request of SYSCLK, this patch
configure the polarity from the DT for the board.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/mach-tegra/pmc.c diff | blob | history
Beck SC1x5 Kernel