The qspi clock divisor is incorrectly set to twice the value it should
have, possibly because it has been computed based on PLL1 as the clock
parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal
frequencies, not the divisor values). Fix it.
This bug introduced in v3.14-rc1 breaks various devices on the Lager and
Kolesh shmobile boards and should thus be considered as a regression for
which a fix during the -rc series is appropriate.