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ASoC: Intel: Skylake: Disable SRAM Retention before D3
authorDharageswari R <dharageswari.r@intel.com>
Fri, 3 Jun 2016 12:59:37 +0000 (18:29 +0530)
committerMark Brown <broonie@kernel.org>
Tue, 7 Jun 2016 13:19:11 +0000 (14:19 +0100)
commit51a01b8c2ea632ed9a57f98c234a0cd9dafe181a
tree7c13c502568b2af9cfce3f34f477deaeaad586d4tree | snapshot
parent1ae7ca041a460502b0f9877d84d0f0d9bed9cb72commit | diff
ASoC: Intel: Skylake: Disable SRAM Retention before D3

SW needs to set the PGCTL.LSRMD = 1 to disable LPSRAM retention
feature,otherwise it may lead to SRAM ECC Errors.

Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/intel/skylake/skl.c diff | blob | history
sound/soc/intel/skylake/skl.h diff | blob | history
Beck SC1x5 Kernel