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(parent: 8364f5d) | patch
clk: tegra: initialise parent of uart clocks
authorLaxman Dewangan <ldewangan@nvidia.com>
Tue, 12 Feb 2013 15:17:59 +0000 (20:47 +0530)
committerStephen Warren <swarren@nvidia.com>
Wed, 13 Feb 2013 18:17:03 +0000 (11:17 -0700)
commit527fad1bc519df8eedd397482febb51526e5d987
tree003feaff3289f9d27292d2332710e951f142ea25tree | snapshot
parent8364f5d96509e206f02a74bbdc2d4e3742cdefe4commit | diff
clk: tegra: initialise parent of uart clocks

Initialise the parent of UARTs to PLLP and disabling clock by
default.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
drivers/clk/tegra/clk-tegra20.c diff | blob | history
drivers/clk/tegra/clk-tegra30.c diff | blob | history
Beck SC1x5 Kernel