ENGR00229441 MX6SL-Reset MMDC read FIFO in low power IDLE

ENGR00229441 MX6SL-Reset MMDC read FIFO in low power IDLE

MMDC can clock in bad data due to the glitches caused by
changing the setting of various DDR IO pads in low power
IDLE to save power. Solution is to reset the MMDC read FIFO
before the DDR exits self-refresh.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>