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(parent: b87bf25) | patch
drm/i915: Replace hardcoded cacheline size with macro
authorChris Wilson <chris@chris-wilson.co.uk>
Wed, 9 Apr 2014 08:19:40 +0000 (09:19 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 22 Apr 2014 19:18:04 +0000 (21:18 +0200)
commit5ed4c83bfc317ad635e09ec7dafb790ce9538377
tree8b54a2fe249b5fe7f023686735e5fcd69479afdatree | snapshot
parentb87bf259e126a18e9acc5e8a9a878c8e30666993commit | diff
drm/i915: Replace hardcoded cacheline size with macro

For readibility and guess at the meaning behind the constants.

v2: Claim only the meagerest connections with reality.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | history
Linux kernel for KaRo TX COM modules