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(parent: 12a5c49) | patch
MIPS: Add printing of ES bit for Imgtec cores when cache error occurs.
authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Thu, 10 Oct 2013 08:58:59 +0000 (09:58 +0100)
committerJohn Crispin <blogic@openwrt.org>
Tue, 14 Jan 2014 11:48:26 +0000 (12:48 +0100)
commit5ed91298a7ac16ca90f8986bfce683aefdfccbf4
tree892719fbc9899986f62db247b8915101abecb5f6tree | snapshot
parent12a5c494cc4c31a61a9704f5a773d5fbcd15bb45commit | diff
MIPS: Add printing of ES bit for Imgtec cores when cache error occurs.

The cacheer register is always implemented in the same way in the
MIPS32r2 Imgtec cores so print the ES bit when an cache error
occurs.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6041/
arch/mips/kernel/traps.c diff | blob | history
Linux kernel for KaRo TX COM modules