ENGR00214607 [MX6]Fix CPUFreq change flow issue

ENGR00214607 [MX6]Fix CPUFreq change flow issue

Previous flow when we change PLL1_SW_CLK from 400M
PFD to PLL1_MAIN_CLK is as below:

1. move PLL1_SW_CLK from 400M PFD to PLL1_MAIN_CLK;
2. change PLL1_MAIN_CLK's freq if necessary;

There is chance that the PLL1_MAIN_CLK freq is higher
than what we want, then after step1, system may hang as
we use low voltage to run high freq.

The correct flow should be as below:

1. make sure PLL1_MAIN_CLK is enabled;
2. make sure pLL1_MAIN_CLK freq is what we want;
3. move PLL1_SW_CLK from 400M PFD to PLL1_MAIN_CLK.

Signed-off-by: Anson Huang <b20788@freescale.com>