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ENGR00180775 IPUv3:Change pixel clock disabling sequence
authorLiu Ying <Ying.Liu@freescale.com>
Wed, 25 Apr 2012 06:34:31 +0000 (14:34 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:34:29 +0000 (08:34 +0200)
commit60589a58d26647f4ec17013e092bb36ed7227449
tree533d2ec0b8cf518e696420b983c15601e17b134ftree | snapshot
parent642616ffe8b93de625ef2c19c26daf81c5ea29aecommit | diff
ENGR00180775 IPUv3:Change pixel clock disabling sequence

This patch postpones pixel clock and its parent clock(if
the parent clock usecount is 1) disabling time point
until DC/DP/DI enable bits are cleared in IPU_CONF
register to prevent LVDS display channel starvation for
some special LVDS display video mode.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
drivers/mxc/ipu3/ipu_common.c diff | blob | history
drivers/mxc/ipu3/ipu_disp.c diff | blob | history
Linux kernel for KaRo TX COM modules