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(parent: 7556423) | patch
perf_counter: add comment to barrier
authorPeter Zijlstra <a.p.zijlstra@chello.nl>
Fri, 13 Mar 2009 11:21:30 +0000 (12:21 +0100)
committerIngo Molnar <mingo@elte.hu>
Mon, 6 Apr 2009 07:29:32 +0000 (09:29 +0200)
commit60b3df9c1e24a18aabb412da9905208c5f04ebea
tree2c132d1a82648b176f8662cea32f51c208517dd5tree | snapshot
parent755642322aa66fbc5421a35fd3e1733f73e20083commit | diff
perf_counter: add comment to barrier

We need to ensure the enabled=0 write happens before we
start disabling the actual counters, so that a pcm_amd_enable()
will not enable one underneath us.

I think the race is impossible anyway, we always balance the
ops within any one context and perform enable() with IRQs disabled.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perf_counter.c diff | blob | history
Beck SC1x5 Kernel