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(parent: d608254) | patch
MIPS: Ensure cache ops complete in mips_cache_reset
authorPaul Burton <paul.burton@imgtec.com>
Wed, 21 Sep 2016 10:18:59 +0000 (11:18 +0100)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Wed, 21 Sep 2016 13:04:04 +0000 (15:04 +0200)
commit639200f6a0dcfe67e4c923b6108703e192946388
tree2c086874eab5ecabfe7b0aac920d8608d5fbbc72tree | snapshot
parentd608254b0aa23607df1dcb5a7ca07de9a8ec9bb0commit | diff
MIPS: Ensure cache ops complete in mips_cache_reset

Ensure that cache operations complete before returning from
mips_cache_reset by placing a completion barrier (sync instruction)
before the return. Without this there is no guarantee that the cache ops
will complete before any subsequent memory accesses, since they are
indexed cache ops & thus not implicitly ordered with memory accesses.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
arch/mips/lib/cache_init.S diff | blob | history
UBoot for KaRo TX COM modules