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(parent: bd2724c) | patch
ENGR00179685 MX6 clock:Cleanup LDB DI parent clock
authorLiu Ying <Ying.Liu@freescale.com>
Mon, 16 Apr 2012 04:40:37 +0000 (12:40 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:34:27 +0000 (08:34 +0200)
commit6925a6c650fe12d4f789798da4457fd4aead4250
treecba800f50a0383afeba38ee69f398b3b26d1b6cdtree | snapshot
parentbd2724c159e09622e2578e002e1975cf657f2fb7commit | diff
ENGR00179685 MX6 clock:Cleanup LDB DI parent clock

According to ticket TKT071080, 0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1.
However, MX6DL uses mmdc_ch1 as LDB DI parent clock.
This patch corrects the LDB DI parent clock setting.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
arch/arm/mach-mx6/clock.c diff | blob | history
Linux kernel for KaRo TX COM modules