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MIPS: Netlogic: Avoid unnecessary cache flushes
authorJayachandran C <jayachandranc@netlogicmicro.com>
Tue, 23 Aug 2011 08:05:51 +0000 (13:35 +0530)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 8 Nov 2011 12:36:05 +0000 (12:36 +0000)
commit6a4b190b272437a0170264b5de25229bcf71fd0d
tree231f5a0666edef4857c45ef0b30799731eb641d1tree | snapshot
parentf96f38184c2c2f99614671a2e9b7bf21beefcc4fcommit | diff
MIPS: Netlogic: Avoid unnecessary cache flushes

XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache
flushes.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2729/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h diff | blob | history
Linux kernel for KaRo TX COM modules