ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks

ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks

The i.MX6 Reference Manual requires PLLs to be powered down before
changing its rate.  Let's add flag CLK_SET_RATE_GATE for PLLs and
audio/video dividers to enforce the check at clock core level.  So any
clk_set_rate() call from clients on these clocks will fail if the clocks
are not disabled and unprepared.

shawn.guo: cherry-pick commit 763c47cb3684 from imx_3.10.y

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>