]> git.karo-electronics.de Git - karo-tx-linux.git/commit
drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 14 Feb 2013 19:53:51 +0000 (21:53 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Sun, 17 Feb 2013 18:06:44 +0000 (19:06 +0100)
commit7040111b41924424a976a3217fa6bccf5a4c2c3f
tree3ec0b7959c08dabad437fd7c32bb6913909a7b0a
parent0568d08790bff87652aabed3b0f534fbc0a6f651
drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+

The bit controlling whether PIPE_CONTROL DW/QW write targets
the global GTT or PPGTT moved moved from DW 2 bit 2 to
DW 1 bit 24 on IVB.

I verified on IVB that the fix is in fact effective. Without the fix
none of the scratch writes actually landed in the pipe control page.
With the fix the writes show up correctly.

v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c