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Hexagon: Implement basic cache-flush support
authorRichard Kuo <rkuo@codeaurora.org>
Tue, 13 Sep 2011 00:38:02 +0000 (10:38 +1000)
committerStephen Rothwell <sfr@canb.auug.org.au>
Tue, 13 Sep 2011 00:38:02 +0000 (10:38 +1000)
commit707f461c3c061490c98bc2860a600c8b3ae7a35e
tree24f3a7b63163f3e3ab2e1ef88171414729d805a0tree | snapshot
parent93658c8b7120e4b3f323d026caa52a7647bb3837commit | diff
Hexagon: Implement basic cache-flush support

We have separate I/D caches.  Data caches are physically indexed.

Signed-off-by: Richard Kuo <rkuo@codeaurora.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
arch/hexagon/include/asm/cache.h [new file with mode: 0644] blob
arch/hexagon/include/asm/cacheflush.h [new file with mode: 0644] blob
arch/hexagon/mm/cache.c [new file with mode: 0644] blob
Linux kernel for KaRo TX COM modules