We add 2 Suspend to RAM modes:
- A3SM PLL0 on/off: Power domain A3SM that contains the ARM core
and the 2nd level cache with either PLL0 on
or off
As the suspend to memory mechanism we use A3SM PLL off. A3SM PLL on
is included here too, so CPUIdle can use both power down modes (not
included in this patch).
The setup of the SYSC regarding the external IRQs is taken from
pm-sh7372.c from Magnus Damm.