EDAC: Handle csrow/channel on csbased MCIs differently

EDAC: Handle csrow/channel on csbased MCIs differently

The csrow and channel on csbased memory controllers get reported in the
top_layer and mid_layer arguments. If we rely on the dimm->csrow, we
get wrong csrows incremented in sysfs. For example, for an injection to
csrow 1 on MCT 1:

[ 5448.720258] EDAC MC1: 1 CE on mc#1csrow#1channel#1 (csrow:1 channel:1 page:0x827c43 offset:0xca0 grain:0 syndrome:0x1c6)

we get

[ 5448.720244] EDAC DEBUG: edac_mc_handle_error: rank csrows map: (3,0)
[ 5448.720248] EDAC DEBUG: edac_mc_handle_error: csrow/channel to increment: (3,0)

csrow 3, channel 0 to increment mc1/csrow3/ce_count sysfs counter.

Fix this by reading the csrow number directly.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>