Implement enable/disable for Display C6 state

Implement enable/disable for Display C6 state

This patch just implements the basic enable and disable
functions of DC6 state which is needed for SKL platform.

Its important to load SKL CSR program before calling enable.

DC6 is a deeper power saving state where hardware dynamically
disables power well 0 and saves the associated registers.
DC6 can be entered when software allows it, the conditions
for DC5 are met, and the PCU allows DC6.
DC6 cannot be used if the backlight is being driven from the
display utility pin.

Its better to configure display engine to have power well 2
disabled before getting into DC6 enable function. Hence rpm
framework will ensure to check status of power well 2 and DC5
before calling skl_enable_dc6.

v2: Replace HAS_ with IS_ check as per Daniel's review comments

v3: Cleared the bits dc5/dc6 enable of DC_STATE_EN register
before setting them as per Satheesh's review comments.

v4: No need to call gen9_disable_dc5 inside enable sequence of
DC6, as its already take care above.

v5: call POSTING_READ for every write to a register to ensure that
its written immediately.
Call intel_prepare_ddi during DC6 exit as it's required on low-power exit.

v6: Protect DC6-enabling-disabling functionality with locks to synchronize
with CSR-loading code.

v7: Remove grabbing CSR-related mutex in skl_enable/disable_dc6 functions as
    deferred DC5-enabling functionality is now removed.

v8: Remove 'Disabling DC5' from the debug comment during DC6 enabling as when
    DC6 is allowed, DC5 is not programmed at all.

v9:
- Rebase to latest.
- Move all DC6-related functions from intel_display.c to intel_runtime_pm.c.

v10: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)

Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>