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ENGR00160492: MX6-Disable PLL1 when CPU clk is below 400MHz.
authorRanjani Vaidyanathan <ra5478@freescale.com>
Wed, 19 Oct 2011 19:38:19 +0000 (14:38 -0500)
committerOliver Wendt <ow@karo-electronics.de>
Mon, 30 Sep 2013 12:09:49 +0000 (14:09 +0200)
commit75c62ee7914952ecdd8ff31b7b97839eef94006c
treee69364c38524362f78dec34886460b286ae4257atree | snapshot
parent7c2d5bcd2b116894f09f573c89bf5a5c9435bcb7commit | diff
ENGR00160492: MX6-Disable PLL1 when CPU clk is below 400MHz.

When CPU frequency is below 400MHz (due to CPUFREQ or dvfs-core), we can source
pll1_sw_clk from PLL2_PFD_400M and disable PLL1. This can save some power.

Fixed warnings in dvfs_core driver.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
arch/arm/mach-mx6/clock.c diff | blob | history
arch/arm/mach-mx6/cpu_op-mx6.c diff | blob | history
arch/arm/plat-mxc/dvfs_core.c diff | blob | history
Linux kernel for KaRo TX COM modules