ENGR00176160 [MX6]Correct PLL1 freq change flow

ENGR00176160 [MX6]Correct PLL1 freq change flow

Previous PLL1 freq change is done by switching CPU clock
to 400M pfd or 24M OSC, then modifying
PLL1 div directly, and switch back CPU clock immediately,
it will result in CPU clock stop during PLL1 hardware lock
period, thus, DRAM FIFO may blocked by the data CPU
requested before PLL1 clock changed, and it will block other devices
accessing DRAM, such as IPU, VPU etc. It will cause
underrun or hang issue. We should wait PLL1 lock, then switch
back.

Signed-off-by: Anson Huang <b20788@freescale.com>