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(parent: 1dfbec3) | patch
clk: rockchip: add 400MHz to rk3066 clock rates table
authorPaweł Jarosz <paweljarosz3691@gmail.com>
Fri, 4 Nov 2016 13:10:56 +0000 (14:10 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Sat, 5 Nov 2016 22:11:01 +0000 (23:11 +0100)
commit82e56393a80b99cf8986616447d71cbcff90e9d1
tree3ff176f7fa80fb65d008cd8816709b7bedc89368tree | snapshot
parent1dfbec3905548a0cbc820a62e1d8adee1c80bd41commit | diff
clk: rockchip: add 400MHz to rk3066 clock rates table

We need this to init PLL_CPLL to 400MHz at boot.

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3188.c diff | blob | history
Beck SC1x5 Kernel