]> git.karo-electronics.de Git - linux-beck.git/commit
clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate
authorRhyland Klein <rklein@nvidia.com>
Thu, 18 Jun 2015 21:28:34 +0000 (17:28 -0400)
committerThierry Reding <treding@nvidia.com>
Fri, 20 Nov 2015 17:07:28 +0000 (18:07 +0100)
commit86c679a52294d4c4b989903a75e31495c04d688a
tree784a8f92ecd5315cb7cfddecb4f4a0e4369886f3
parentfde207eb15115f1081e589267ebdf442aa54cda5
clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate

This removes the conversion from pdiv to hw, which is already taken
care of by _get_table_rate before this code is run. This avoids
incorrectly converting pdiv to hw twice and getting the wrong hw value.

Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while
setting all the other fields.

In order to prevent regressions on earlier SoC generations, all of the
frequency tables need to be updated so that they contain the actual
divider values. If they contain hardware values these would be converted
to hardware values again, yielding the wrong value.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: fix regressions on earlier SoC generations]
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-pll.c
drivers/clk/tegra/clk-tegra114.c
drivers/clk/tegra/clk-tegra124.c
drivers/clk/tegra/clk-tegra20.c
drivers/clk/tegra/clk-tegra30.c