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MIPS: introduce CPU_R4K_CACHE_TLB
authorFlorian Fainelli <florian@openwrt.org>
Tue, 31 Jan 2012 17:18:45 +0000 (18:18 +0100)
committerJohn Crispin <blogic@openwrt.org>
Tue, 21 Aug 2012 17:15:16 +0000 (19:15 +0200)
commit893f983c123dfc9235fa148486f801cdd3a28d7d
tree8c38a9050c979e498be3cef75bd5c98b8e800111tree | snapshot
parente2f59f9412136704305d9a942ece9d852efff0afcommit | diff
MIPS: introduce CPU_R4K_CACHE_TLB

R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/
Signed-off-by: John Crispin <blogic@openwrt.org>
arch/mips/Kconfig diff | blob | history
arch/mips/mm/Makefile diff | blob | history
Linux kernel for KaRo TX COM modules