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(parent: 5b0dde9) | patch
clk: tegra30: Don't wait for PLL_U lock bit
authorTuomas Tynkkynen <ttynkkynen@nvidia.com>
Wed, 28 Aug 2013 15:18:47 +0000 (18:18 +0300)
committerMike Turquette <mturquette@linaro.org>
Thu, 29 Aug 2013 02:08:09 +0000 (19:08 -0700)
commit89ac8567b97fea558238c4bb73637471f9197813
treeaae20760c9d0163f2ae08484dd6b544d946a7efatree | snapshot
parent5b0dde99e8a9971030b36096ee1dc85a1a12ff57commit | diff
clk: tegra30: Don't wait for PLL_U lock bit

The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/tegra/clk-tegra30.c diff | blob | history
Linux kernel for KaRo TX COM modules