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(parent: 31adb06) | patch
ARM: CSR: initializing L2 cache
authorRongjun Ying <rongjun.ying@csr.com>
Fri, 8 Jul 2011 09:40:14 +0000 (02:40 -0700)
committerBarry Song <21cnbao@gmail.com>
Fri, 8 Jul 2011 23:21:53 +0000 (07:21 +0800)
commit89e162afd37caa6acab4e05b6e9e9fad6235381e
treeac5dafe6664ab1e5fab867fcef7d8a7c685d8f78tree | snapshot
parent31adb06f9d68f9d033284c9ab0e264b2d581bcebcommit | diff
ARM: CSR: initializing L2 cache

Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <baohua.song@csr.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
arch/arm/mach-prima2/Makefile diff | blob | history
arch/arm/mach-prima2/l2x0.c [new file with mode: 0644] blob
Beck SC1x5 Kernel