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ENGR00181191 MX6: set ipu2_clk parent from pll2_pfd_400M
authorWayne Zou <b36644@freescale.com>
Fri, 27 Apr 2012 06:31:55 +0000 (14:31 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:34:31 +0000 (08:34 +0200)
commit89f4ca2c871bb59f65cb894102fb28efbb04c9b9
tree9159f67ecb8c83dc70fbac061ecc7b2d220ea862tree | snapshot
parent1acc24535fbf5694175fccc36da8e3889b4ba764commit | diff
ENGR00181191 MX6: set ipu2_clk parent from pll2_pfd_400M

On mx6dl, set ipu2_clk's parent from pll2_pfd_400M.
On mx6q, ipu2_clk's parent from mmdc_ch0_axi_clk, and it is 264MHz by default.

Signed-off-by: Wayne Zou <b36644@freescale.com>
arch/arm/mach-mx6/clock.c diff | blob | history
Linux kernel for KaRo TX COM modules