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amd64_edac: Add a fix for Erratum 505
authorBorislav Petkov <borislav.petkov@amd.com>
Mon, 19 Sep 2011 15:34:45 +0000 (17:34 +0200)
committerBorislav Petkov <borislav.petkov@amd.com>
Fri, 30 Sep 2011 14:36:38 +0000 (16:36 +0200)
commit8afd8900d8857d5dc1037cd43ffafee9c2bef430
treefbc652a29efee4443326e06ec89b187de439a2ectree | snapshot
parentaafa38b89647c2e7a40aadf2b653e08880a79859commit | diff
amd64_edac: Add a fix for Erratum 505

When accessing the scrub rate control register (F3x58) on F15h, the DRAM
controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the
scrub rate configuration can take effect. See Erratum 505 in the AMD
F15h revision guide for more details.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
drivers/edac/amd64_edac.c diff | blob | history
Linux kernel for KaRo TX COM modules