ENGR00289268 [iMX6x] Ensure there is no TLB miss when DDR is in self-refresh

ENGR00289268 [iMX6x] Ensure there is no TLB miss when DDR is in self-refresh

During DDR frequency change code or in low power IDLE code (in iMX6SL),
we need to ensure that all register addresses accessed in the IRAM
code are in the TLB. There should be no TLB walks when DDR is in self-refresh.
To ensure this flush the TLB before DDR frequency change and before
low power IDLE (only iMX6SL) procedures.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>