ENGR00154211 [MX6]Add workaround for wdog errata

ENGR00154211 [MX6]Add workaround for wdog errata

Errata number:TKT039676

WDOG sw reset is generated by writing to its
control register. WDOG's reset is activated by
ipg_clk_s, and is de-activated (later) by a
synchronized CKIL (32KHz clock). On the other
hand SRC samples the WDOG reset with an
unsynchronized CKIL clock. If the write to WDOG
control register happens between the edges of
unsynchronized and synchronized CKIL clocks SRC
will miss the wdog reset pulse.

Workaround: write wdog control register twice.

Signed-off-by: Anson Huang <b20788@freescale.com>