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ENGR00172360-1 - MXC HDMI: New TO1.1 PLL5/PLL4 dividers not set up in clock co
authorDanny Nold <dannynold@freescale.com>
Thu, 19 Jan 2012 20:53:51 +0000 (14:53 -0600)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:33:50 +0000 (08:33 +0200)
commit9058746ac13a00dbf6d9c0b1ae574288c90fc187
treea17db6b22d3506028f1c440e9fac7d9c00b4d16etree | snapshot
parent84602a7181163479678270ab1bad487198611275commit | diff
ENGR00172360-1 - MXC HDMI: New TO1.1 PLL5/PLL4 dividers not set up in clock co

Update get_rate, set_rate, and round_rate for audio_video PLLs
to account for new dividers added for MX6Q TO1.1.  Since default value
for one of these dividers is 4, this is important for function of clocks
derived from PLL4 and PLL5.

Signed-off-by: Danny Nold <dannynold@freescale.com>
arch/arm/mach-mx6/clock.c diff | blob | history
arch/arm/mach-mx6/crm_regs.h diff | blob | history
Linux kernel for KaRo TX COM modules