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(parent: ccf1c86) | patch
drm/i915: add LCPLL control registers
authorEugeni Dodonov <eugeni.dodonov@intel.com>
Thu, 29 Mar 2012 15:32:35 +0000 (12:32 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 9 Apr 2012 16:04:04 +0000 (18:04 +0200)
commit90e8d31c53890064962f1154405e1034be7ec9a1
tree6306c85da1d7f710eba351264cc582e177cef527tree | snapshot
parentccf1c867ce049bf27a1f7172f1a91820b3ceb6e5commit | diff
drm/i915: add LCPLL control registers

Those are used to control the display core clock.

v2: change the enable bit setting, spotted by Rodrigo Vivi.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
Beck SC1x5 Kernel