ENGR00214337 MX6: Enable AXI cache for VDOA/VPU/IPU and set IPU high priority

ENGR00214337 MX6: Enable AXI cache for VDOA/VPU/IPU and set IPU high priority

set IPU AXI-id0 Qos=0xf(bypass) and  AXI-id1 Qos=0x7,
mx6q use AXI-id0 for IPU display channel, it should has
highest priority(bypass), and AXI-id1 for other IPU channel,
it has high priority.

Also, clear OCRAM_CTL bits to disable OCRAM read/write pipeline control.

Signed-off-by: Wayne Zou <b36644@freescale.com>