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(parent: 7ff4db0) | patch
ARM: tegra: change pll_p_out4's rate to 24MHz
authorStephen Warren <swarren@nvidia.com>
Thu, 12 Apr 2012 20:13:05 +0000 (14:13 -0600)
committerStephen Warren <swarren@nvidia.com>
Wed, 25 Apr 2012 21:22:09 +0000 (15:22 -0600)
commit9abafa021e223f04d6589ee2b977bbaf2e1f1367
tree6029d68e9dc837b40677282e459fc807aa76e581tree | snapshot
parent7ff4db0967bd7d617c77dc5a66c0d95166277817commit | diff
ARM: tegra: change pll_p_out4's rate to 24MHz

pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.

Remove board-paz00.c's now-duplicate initialization of this clock.

Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/mach-tegra/board-paz00.c diff | blob | history
arch/arm/mach-tegra/common.c diff | blob | history
Linux kernel for KaRo TX COM modules